In a circuit for providing a bias for a field-effect transistor (FET) in a transistor amplifier, it is desirable to provide a bias voltage for the gate of the transistor which results in a gm that is independent of power supply voltage fluctuations. Conventional bias circuits suffer from degraded performance when built with short-channel FETs, which, to a greater extent than long-channel FETs, exhibit drain-induced barrier lowering (DIBL). This DIBL causes the bias voltage generated by a conventional circuit to result in a gm that varies significantly with power supply voltage. Thus, there is a need for a bias circuit which generates a bias voltage that results in a gm that varies to an acceptably small extent with changes in the power supply voltage, and which can be constructed with short-channel FET devices.